In a microcomputer system, a technology is known which tries to reduce a processing load of the CPU by transferring data between peripheral devices including a memory without the aid of a microprocessor (CPU: Central Processing Unit) serving as a control center. In this case, a DMA (Direct Memory Access) controller, which is programmable by the CPU, carries out the data transfer control.
In addition, to further improve a throughput in the foregoing microcomputer system, a DMA controller is known which stores in a ROM instruction groups corresponding to specific requests from the CPU, and carries out data transfer control between peripheral devices in accordance with a specific instruction read out of the ROM (see Patent Document 1, for example).
Furthermore, to transfer data between a peripheral device and a main storage having data bus widths different from each other without the aid of the CPU, a DMA controller is known which transfers data by adjusting the data width to that of the device having the broader bus width (see Patent Document 2, for example). Here, the term “data bus width” refers to the amount of data that can be sent simultaneously per transfer.    Patent Document 1: Japanese Patent Laid-Open No. 2000-215152.    Patent Document 2: Japanese Patent Laid-Open No. 5-94404/1993.
According to the technology disclosed in the foregoing Patent Document 1, the data transfer is automated and the involvement of the CPU in it can be reduced to a minimum. However, as for the processing contents the peripheral device at a transfer destination requests for at a transfer such as data transfer between peripheral devices having different data bus widths, they become a load of the CPU so that the reduction in the processing load of the CPU is not yet enough.
On the other hand, according to the technology disclosed in Patent Document 2, since the DMA controller adjusts the data bus widths at the DMA transfer between the peripheral device and main storage, it can eliminate the foregoing processing load of the CPU. However, a problem still remains in that it can only cope with the case where the data bus width is an integer multiple of the data bus width of the peripheral device.
The present invention is implemented to solve the foregoing problems. Therefore it is an object of the present invention to provide a data transfer control device and a computer system capable of improving the throughput by further reducing the processing load of the CPU by constructing a device for performing operations requested by a transfer destination peripheral device on the data read out of a transfer source peripheral device.